Diseño y caracterización de criptocircuitos seguros y resistentes a ataques físicos

Resum

Every day, people all over the world use electronic devices to store or exchange private information with each other. Confidentiality and privacy is a right against possible intruders, so security in new technologies is an important factor that requires the attention of the scientific community. Electronic devices considered "secure", in fact any electronic device for use in telecommunications or handling relevant information, make use of cryptography to ensure the confidentiality, authentication and integrity of the data processed. These cryptographic devices implement mathematically secure algorithms, but due to their physical implementation, they can reveal sensitive information due to data leaks during their normal operation, which can be exploited by an attacker to reveal the device’s secret key. These attacks, known as side channel attacks, are very effective and exploit information such as power consumption, electromagnetic radiation or timing, among others, to reveal the secret key. The scientific community has focused its efforts on the design of countermeasures to prevent this type of attack. The main objective of this Thesis is to increase the security of hardware cryptographic devices against side channel attacks. To achieve this objective, the following 3 tasks have been carried out: 1. Vulnerability measurements of a cryptographic device (execution of attacks and security metrics). 2. Proposals for countermeasures. 3. Security assessment. To measure the vulnerability of cryptographic devices, attacks based on power consumption, electromagnetic attacks or the use of other metrics such as t-test have been implemented. To test the effectiveness of the attacks, they have been performed on private key systems, using block cipher demonstrators (AES and a part of the KASUMI algorithm) and stream ciphers (Trivium). These measurements have been carried out both in simulation environments and experimentally on ASIC or FPGA implementations. In addition, different alternative metrics and tests have been evaluated in order to evaluate security at different stages of design, as well as to determine the level of security without having to carry out a complete attack. On the other hand, different methodologies have been proposed for the design of countermeasures against side channel attacks applied at different levels of abstraction. The proposals at the transistor level consist of modifying the structures of the designed logic cells to obtain an equal power consumption independently of the processed data. At the gate level, different techniques are proposed that vary the timing of the circuit, thus modifying the security levels achieved by the designed cryptocircuits. These countermeasures are complementary and therefore both applicable in the same design. Finally, once the two previous tasks had been completed, a design stage has been undertaken where the case studies implementing cryptographic blocks have been integrated into an ASIC, applying the countermeasures proposed throughout the development of the Thesis. The characterization of the different case studies will experimentally determine the security gain obtained by each countermeasure.