RAUL
JIMENEZ NAHARRO
PROFESOR TITULAR DE UNIVERSIDAD
Ángel
Barriga Barros
Publications by the researcher in collaboration with Ángel Barriga Barros (3)
1998
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Design and characterisation of a CMOS VLSI self-timed multiplier architecture based on a bit-level pipelined-array structure
IEE Proceedings: Circuits, Devices and Systems, Vol. 145, Núm. 4, pp. 247-253
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Efficient self-timed circuits based on weak NMOS-trees
Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, Vol. 3, pp. 179-182
1995
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New CMOS VLSI linear self-timed architectures
Asynchronous Design Methodologies, Working Conference Proceedings