Publications in collaboration with researchers from Instituto de Microelectrónica de Sevilla (3)

2002

  1. High-performance edge-triggered flip-flops using weak-branch differential latch

    Electronics Letters, Vol. 38, Núm. 21, pp. 1243-1244

2001

  1. Practical low-cost CPL implementations of threshold logic functions

    Proceedings of the IEEE Great Lakes Symposium on VLSI

1998

  1. Design and characterisation of a CMOS VLSI self-timed multiplier architecture based on a bit-level pipelined-array structure

    IEE Proceedings: Circuits, Devices and Systems, Vol. 145, Núm. 4, pp. 247-253