Publicacions en què col·labora amb Ángel Barriga Barros (3)

1998

  1. Design and characterisation of a CMOS VLSI self-timed multiplier architecture based on a bit-level pipelined-array structure

    IEE Proceedings: Circuits, Devices and Systems, Vol. 145, Núm. 4, pp. 247-253

  2. Efficient self-timed circuits based on weak NMOS-trees

    Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, Vol. 3, pp. 179-182

1995

  1. New CMOS VLSI linear self-timed architectures

    Asynchronous Design Methodologies, Working Conference Proceedings